Random hardware failures are handled by failure rates and redundancy. Systematic failures come from errors in specification, design, manufacture, installation, software or maintenance: they are not random and cannot be averaged away. A device's systematic capability (SC 1 to 4) states the SIL up to which its development process is judged adequate to keep such failures low.
How it limits a SIF
The achieved SIL of a subsystem cannot exceed the SC of its elements. In First Out AI the lowest SC in the function caps the achieved SIL, alongside probability and fault tolerance.
There is one recognised way to combine elements: two independent, diverse elements of SC N in a redundant arrangement can be argued for SC N+1 for the combination, provided the diversity is real (different technology or design).
Where SC comes from
- A certificate from an accredited body, stating SC for the defined use.
- For devices without certificates, the process sector allows selection based on prior use: documented evidence of satisfactory operation in a similar environment and application, with a management system that tracks failures. This evidence must be recorded and reviewed.
Common mistakes
- Assuming a SIL 3 certified logic solver makes the whole function SIL 3 capable.
- Using a device outside the conditions stated in its safety manual (the certificate no longer applies).
- Forgetting the application program: systematic failures in the trip logic are controlled by the programming rules, reviews and testing described in the SRS.
In First Out AI
Set SC per group. The result shows "Systematic capability" with the lowest element; the AI lists it when SC is below the target.
Written for First Out AI as engineering guidance. It supports engineering work and does not replace it; check every value against your standards, certificates and company rules with a competent functional safety engineer.